for VG = 0 V, .2 V, .4 V, ...., 1.4 V
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Note that you can make the p-channel JFET characteristic curves look like the common n-channel JFET curves just by rotating the pJFET plot by 180°. In swapping n-channel for p-channel so nJFET pJFET, we've reversed the direction of current flows (so currents are negative -- flowing out of the drain in a pJFET) and the required supply voltage becomes negative for a pJFET.
That is to say that the pJFET is designed for negative power supplies and out-flowing (negative) drain currents -- the opposite of nJFETs.
The behavior of a p-channel junction field-effect transistor (pJFET) is largely controlled by the voltage at the gate (usually a positive voltage). For the usual drain-source voltage drops (i.e., the saturation region: negative voltages from a few volts down to some breakdown voltage) the drain current (ID) is nearly independent of the drain-source voltage (VDS), and instead depends on the gate voltage (VG). (This is unusual behavior: usually more voltage produces to more current, but here the current only increases slightly with increasing VDS.) The transconductance, i.e., the ratio of the change in drain current to change in gate voltage, often denoted by g or yfs, is
g = yfs = ID/VG
In the simplest approximation the characteristic curves of a nJFET are a set of flat lines:
Each (flat) curve shows that ID doesn't change with changing VDS. The different levels show that ID does depend on VG. The spacing of the constant-ID curves is usually not constant, instead ID depends quadratically on VG:
where the threshold (or pinch-off) voltage VTO and K are constants. The maximum (negative) drain current (which occurs at zero-gate voltage, i.e., VG=0) is denoted IDSS. As VG increases towards VTO the drain current approaches zero. The value of K can be determined from IDSS and VTO:
IDSS = K(VTO-0)2
A slightly more complicated approximation takes into account the sloping of the characteristic curves. In bipolar transistors this is due to the Early Voltage, here a very similar equation results from quite different physics: channel length modulation. The equation looks like:
So in this model all the characteristic curves all have a common x-axis intercept at the large positive voltage 1/. (The dashed curves are far from the active region and in no way represent the actual behavior of the transistor for positive VDS. In fact, the transistor is not designed to be operated with positive VDS.)
(For the above measured 2N5460, 1/ ranges from 140 to 600 V, so the characteristic curves have small but variable slopes.)
The actual relationship between the drain current (ID) and the controlling gate voltage (VG) and drain-source voltage drop (VDS) is some complicated function which we can denote:
Like any function we can approximate it near a particular point using just the first terms of a Taylors expansion:
Clearly these admittance (y) parameters are not constants. For example yos is the slope of a characteristic curve, which is small for voltages near threshold and increases for smaller VG. (Note that slope on an I-V is basically the inverse of the resistance. Thus 1/yos can be described as the output impedance. A typical value for 1/yos would be 100,000 .)
The defining FET parameter -- the transconductance g or yfs -- is not at all constant. To the extent that the drain current depends quadratically on the gate voltage, the transconductance -- which is the derivative: dID/dVG -- depends linearly on VG. Below is the measured relationship: |ID| vs VG for the above 2N5460. Notice that for this device the quadratic approximation for ID fails a full ½ V below VTO. Notice that the quadratic fit to the data would actually have predicted a sign-change in ID (i.e., the minimum for the parabola lies below the x-axis) and that the exponential behavior takes over near where the quadratic approximation would have predicted zero ID The drain current, of course does not change sign, it merely becomes exponentially small.
The characteristic curves focus on the output of the transistor, but we can also consider the behavior of the input. In normal operation the gate is a reversed biased diode, and so IG is essentially zero (which should sound like a huge input resistance). As a result the outputs have little effect on the inputs, but if we follow the traditional analysis the actual functional relationship giving the gate current (IG) from the gate voltage (VG) and drain-source voltage drop (VDS) is some complicated function which we can denote:
Like any function we can again approximate it near a particular point using just the first terms of Taylors expansion:
The small values of yrs and yis shows that the input is largely unaffected by the output and that the input resistance is huge. In fact this input resistance is so large that the capacitance reactance is almost always of greater significance.
Finally it should be noted that in the small VDS region -- before the saturation region -- the FET characteristic curves look like nearly straight lines through the origin. VG controls the slope of these lines, so the FET acts like a variable resistor with a voltage (VG) control. Here is a plot of this region for the above 2N5460:
The spec sheet reports the following values for the 2N5460:
|Forward Transfer Admittance||yfs||1||4||m mhos|
|Output Admittance||yos||-||75||µ mhos|
|Zero-Gate Voltage Drain Current||IDSS||-1||-5||mA|
|Gate Source Cutoff Voltage||VTO||0.75||6.0||V|